Publications

2017

M. De Matteis et al., “An Eight-Channels 0.13- um -CMOS Front End for ATLAS Muon-Drift-Tubes Detectors”, in IEEE Sensors Journal, vol. 17, no. 11, pp. 3406-3415, June1, 1 2017. doi: 10.1109/JSEN.2017.2694606

Abstract: An eight-channel readout front end for Large Hadron Collider (LHC) ATLAS muon-drift-tubes detectors is hereby presented (defined 8 × AFE). The system is composed by the cascade of the analog signal processing front end and the Wilkinson A/D, performing both time-over-threshold and charge measurement. The sensitivity at the output of the analog signal processing chain is 14 mV/fC, while the equivalent-noisecharge is 0.6 fC (~3.38 ke), performing <12-ns preamplifier rise time. These performances have been achieved while managing very high detector parasitic capacitance at the front-end input (~60 pF). Each channel consumes 10 mA from a single 3.3-V supply voltage. In 0.13-µm CMOS, the total area occupancy is 6.3 mm2.

 

F. Ciciotti, A. Baschirotto, C. Buffa and R. Gaggl, “A MOX gas sensors resistance-to-digital CMOS interface with 8-bits resolution and 128dB dynamic range for low-power consumer applications”, 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Giardini Naxos, 2017, pp. 21-24. doi: 10.1109/PRIME.2017.7974097

Abstract: In this paper an interface circuit for MOX gas sensor is presented. It is based on a resistance-to-frequency converter and improves existing solutions in term of performance (offset) and power efficiency. The resistive range covered is 100Ω-1MΩ, with an equivalent 8-bit precision in a total measurement time of 1 second. This corresponds to a dynamic range of about 128dB. Power consumption and design strategy are optimized for mass production targeting consumer applications. The interface is implemented in a standard CMOS 130nm technology with an area of 125000µm2 and 450µA of current consumption.

 

A. D’Amico, C. Djelassi, O. Barbu, D. Haerle, L. Petruzzi and A. Baschirotto, “A mixed-signal multi-functional system for current measurement and stress detection”, 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Giardini Naxos, 2017, pp. 29-32. doi: 10.1109/PRIME.2017.7974099

Abstract: This paper presents the development of a mixed-signal multi-functional system for current measurement and electrical stress detection. The system is composed of a tracking ADC and a double range (a coarse and a fine one) current-steering DAC. The coarse range, designed for the full-scale input values [0A:108A], has a 5b resolution and it is used for the stress detection feature. The fine range is for lower input current values [4A:14A] and it is used for the current measurement, where more accuracy is required. With respect to the full-scale, the resolution of the fine range is 8b.

 

F. Ciciotti, M. De Matteis and A. Baschirotto, “A 0.9V 75MHz 2.8mW 4th-order analog filter in CMOS-bulk 28nm technology”, 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1-4. doi: 10.1109/ISCAS.2017.8050501

Abstract: In this paper a 75MHz 4th order low-pass analog filter in CMOS-28nm is presented. The filter is composed by the cascade of two Active-RC Rauch biquadratic cells. The hereby proposed design manages a very low Vdd/Vth ratio (<;2) for Standard-Process (SP) MOS transistors by means of a dedicated input Common-Mode (CM) feedback circuit (I-CMFB), that operates the OPAMP input differential pair in weak inversion region independently on common mode variations. The single Rauch cell exploits a feed-forward compensated OPAMP, where an improved output CM feedback (O-CMFB) circuit has been adopted reducing this way the parasitic poles of the CM loop, and improving O-CMFB phase margin. The OPAMP has been designed using a folded topology for stable operating point. The design prototype achieves 75MHz-3dB frequency at 2.8mW power consumption from a single 0.9V supply voltage, including also I-CMFB and O-CMFB power. In-band integrated noise is 320uVrms. The filter performs 20dBm and 13dBm IIP3 at 6&11MHz and 50&55&MHz, respectively. Thanks to the very large linearity achieved at edge of the signal pass-band this design has one of the highest Figure-of-Merit for Active-RC filters.

 

M. De Matteis, A. Pipino, F. Resta, A. Pezzotta, S. D’Amico and A. Baschirotto, “A 63-dB DR 22.5-MHz 21.5-dBm IIP3 Fourth-Order FLFB Analog Filter”, in IEEE Journal of Solid-State Circuits, vol. 52, no. 7, pp. 1977-1986, July 2017. doi: 10.1109/JSSC.2017.2693240

Abstract: In this paper, a fourth-order continuous-time follow-the-leader-feedback (FLFB) low-pass (LP) filter is presented. The outstanding FLFB noise behavior is exploited to minimize power consumption. This is achieved by means of customized implementation solutions based on combination of Active-RC/Active-gm-RC cells. The 0.18-µm CMOS prototype performs 22.5-MHz -3 dB LP frequency response. Large linearity and dynamic range were achieved resulting in 21.5-dBm in-band (iB) IIP3 and 87-µVRMS input referred iB integrated noise. The SNR for a -40 dB HD3 is 63 dB. The overall power consumption is 12.6 mW (i.e., 7 mA from a 1.8-V supply). The efficiency of the proposed technique is demonstrated by the achieved figure-of-merit (150.8 dB · J-1), which favourably compares to the state-of-the-art active-RC analog filters.

 

E. A. Vallicelli et al., “Neural spikes digital detector/sorting on FPGA”, 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), Torino, 2017, pp. 1-4. doi: 10.1109/BIOCAS.2017.8325077

Abstract: This paper presents the results of a multidisciplinary experiment where the electrical activity of a rat hippocampus cultured neurons population has been detected and mapped by an advanced FPGA spike-sorting algorithm. Neurons are growth over a silicon chip that is thus capacitively coupled with neuronal cells. Due to noise power coming from bio-silicon interface and analog electronics signal processing, the Action Potentials detection intrinsically needs advanced noise rejection algorithms which are often software/off-line implemented. This approach disables instantaneous detection of neural spikes and cannot be obviously used for real-time electrical stimulation. In this scenario, this paper presents a proper FPGA system able to separate relevant neuronal cells potentials from noise. The FPGA output signals provide real time spatial mapping of biosensor electrical activity, noise and synchronous neural network activity.

 

M. De Matteis, A. Donno, S. Marinaci, S. D’Amico and A. Baschirotto, “A 0.9V 3rd-order single-OPAMP analog filter in 28nm CMOS-bulk”, 2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), Vieste, 2017, pp. 155-158. doi: 10.1109/IWASI.2017.7974237

Abstract: A 3rd order 132MHz cut-off frequency low-pass filter in 2Snm CMOS-bulk technology is presented. Challenges related to the design of analog circuits in 28nm CMOS-bulk process node have been faced and mitigated operating at both architecture and circuit design level. The filter is based on an improved Active-gm-RC structure, where both poles of a Miller-compensated Opamp have been used for synthesizing the 3rd order filter transfer function. The proposed circuit solution enables high linearity (11P3=11.5dBm at 21&22MHz input tones) even if the supply voltage is limited to 0.9V. Moreover, the power consumption is kept as low as 340µW without that the Signal-toNoise ratio (60dB) is penalized. The achieved Figure-of-Merit is 164dB resulting the highest with respect to the state-of-the-art.

 

F. Fary, L. Mangiagalli, A. Pipino, F. Resta, M. De Matteis and A. Baschirotto, “A 200MHz 0.65fJ/(Bit·Search)1.152kb pipeline content addressable memory in 28nm CMOS”, 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Giardini Naxos, 2017, pp. 353-356. doi: 10.1109/PRIME.2017.7974180

Abstract: In this paper a complete design of a Content Addressable Memory (CAM) in bulk-CMOS 28nm technology is presented. The CAM has 64×18 bit resolution, operates at 200MHz and exploits the low power pipeline searching algorithm. Dedicated circuital solutions have been adopted to mitigate the well-known issues in CMOS 28nm-bulk technology (like higher sensitivity to Process-Voltage-Temperature variations, increased gate serie resistance, very low supply voltage vs. threshold voltage, etc). This allows to take advantage of the larger transition frequency available in nm-range technologies and the lower parasitic capacitances. Simulation results (based on post-layout extracted schematic) have been carried out, validating this way the hereby proposed CAM design. Overall average power consumption is 153µW, corresponding to 0.65fJ/(Bit·Search), one of the higher Figure-of-Merit comparing with similar CAM architectures available in literature. Total area occupancy for 1.152kb resolution is 0.015mm2.

C. M. Zhang et al., “Characterization of GigaRad Total Ionizing Dose and Annealing Effects on 28-nm Bulk MOSFETs”, in IEEE Transactions on Nuclear Science, vol. 64, no. 10, pp. 2639-2647, Oct. 2017. doi: 10.1109/TNS.2017.2746719

Abstract: This paper investigates the radiation tolerance of 28-nm bulk n and pMOSFETs up to 1 Grad of total ionizing dose (TID). The radiation effects on this commercial 28-nm bulk CMOS process demonstrate a strong geometry dependence as a result of the complex interplay of oxide and interface charge trapping relevant to the gate-related dielectrics and the shallow trench isolation. The narrowest/longest channel devices have the most serious performance degradation. In addition, nMOSFETs present a limited on-current variation and a significant off-current increase, while pMOSFETs show a negligible off-current change and a substantial on-current degradation. The postirradiation annealing annihilates or neutralizes oxide trapped positive charges and tends to partly recover the degraded device performance. To quantify the effects of TID and postirradiation annealing, parameters including the threshold voltage, the free carrier mobility, the subthreshold swing, and the drain-induced barrier lowering are extracted.

 

J. P. Jansson, P. Keränen, J. Kostamovaara and A. Baschirotto, “CMOS technology scaling advantages in time domain signal processing”, 2017 IEEE International Instrumentation and Measurement Technology Conference (I2MTC), Turin, 2017, pp. 1-5. doi: 10.1109/I2MTC.2017.7969659

Abstract: This paper compares two CMOS technologies, the robust 350nm version and its modern 28nm successor, in terms of time-domain signal processing parameters. The evaluated parameters; propagation delay, delay variation due to process and mismatch fluctuations, sensitivity to noise and area and power usage are crucial especially in measurement devices relying on precise timings, high precision time-to-digital converters, for example. Post-layout simulations show that the modern scaled technology offers superior speed, efficient area usage and low power consumption but suffers from considerable delay mismatch. Therefore applications relying on precise time domain signal processing do not always benefit from technology scaling.

 

M. De Matteis and A. Baschirotto, “A Biquadratic Cell Based on the Flipped-Source-Follower Circuit”, in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 8, pp. 867-871, Aug. 2017. doi: 10.1109/TCSII.2016.2611061

Abstract: This brief presents a novel biquadratic cell (biquad) based on the flipped-source-follower (FSF) circuit. The main idea is to exploit the FSF circuit as a basic building block for a low-pass second-order filter, taking advantage of its well-known strengths, like low-output impedance, low-noise, large in-band linearity, and low power. Thanks to the very essential FSF circuit, the resulting biquad is a power-efficient broad bandwidth stage, with very low-noise performance. In order to validate the biquad design idea, extensive circuital simulation results will be presented. The filter design example synthesizes a third-order low-pass transfer function and consumes 2.3 mW from a single 1.8 V@VDD. Input noise spectral density is 7 nV/vHz. Linearity has been evaluated in terms of IIP3 (25 dBm) and THD (-40 dBc at 380mV0-PEAK output voltage swing, resulting in 62-dB SNR). Hence, a very promising figure-of-merit (i.e., 165 J-1) has been achieved.

 

L. Mangiagalli et al., “15 Mrad ionizing radiation dose effect on GEMINI”, 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Giardini Naxos, 2017, pp. 245-248. doi: 10.1109/PRIME.2017.7974153

Abstract: The GEMINI front-end system that will operate at LoKI experiment at ESS is expected to be exposed to radiation for a Total Ionizing Dose (TID) up to 200krad during Triple-GEM detector usage. Analyzing the effect of ionizing radiation on chip gives important information on its robustness, critical for architecture validation. After irradiation with a total dose of 15 Mrad core elements of GEMINI channels still resulted to be functional. This indicates the possibility of using such devices also in other experiments where it would be exposed to higher TID. The test also highlighted few critical points of the architecture that could be starting point to improve Triple-GEM front-end system radiation hardness.

 

F. Resta et al., “1GigaRad TID impact on 28nm HEP analog circuits”, 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Giardini Naxos, 2017, pp. 225-228. doi: 10.1109/PRIME.2017.7974148

Abstract: The Total Ionizing Dose (TID) levels foreseen after the future upgrade of the CERN Large Hadron Collider (High Luminosity LHC) will heavily influence the performance of the electronics. A TID level of 1GigaRad will be accumulated in the innermost layer of the pixel detector in 10 years of operations, which could damage the readout circuits behavior with important failures in the experiments. To prevent this situation, the choice of a proper technology for the readout ASICs represents a key point. This paper deals with the characterization of single transistors and of an analog circuit, both realized in a TSMC 28nm bulk CMOS technology, after being irradiated with 1 GigaRad TID. nMOS devices result more resistant than pMOS showing a weak degradation of the electrical parameters. Nevertheless, the considerable leakage current increment is not negligible because it could affect analog circuits as that hereby presented. In the proposed analog circuit, the high radiation level induces a 20% gain reduction and an 80% slowdown of the Charge Sensitive Preamplifier time response.

 

M. De Matteis, A. D’Amico, F. Ciciotti and A. Baschirotto, “Closed-loop continuous-time analog filter with almost constant IIP3 over the pass-band”, 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1-4. doi: 10.1109/ISCAS.2017.8050505

Abstract: This paper presents the design of a 4th-order closed-loop continuous-time filter. This filter exploits an improved analog stage that makes linearity performance constant over the entire pass-band frequencies. In other words the filter has same IIP3 at low and at high frequency. Hence the linearity performance are independent on the input tones bandwidth, whereas most of analog filters suffers from poor linearity when loop-gain reduces, i.e. close to the closed-loop poles frequency. In order to validate the hereby proposed design idea a 4th-order 25MHz-3dB bandwidth pseudo-differential filter has been designed and simulated in CMOS 28nm technology. The prototype consumes 820µW from 1V supply voltage and has 15dBm and 13dBm IIP3 at 5&6MHz and 20&21MHz input tones, respectively.

 

M. Riva, E. Vallicelli, A. Baschirotto and M. De Matteis, “Acoustic analog front-end for Bragg-Peak detection in hadron therapy”, 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, 2017, pp. 1-4. doi: 10.1109/BIOCAS.2017.8325223

Abstract: Clinical proton and ions beams for cancer treatment provide maximum energy deposition (Bragg Peak, BP) at the end of their range and practically no dose behind. This enables a more efficient therapeutic option comparing with classical photon-based radiotherapy where maximum energy deposition occurs at the body/tissues interface. Obviously, optimum/minimum-error BP detection and calibration is thus a key aspect of this treatment. This work investigates a promising detection technique, based on the so called (proton) iono-acoustic effect. The BP energy deposition causes a small (mK) heating of the surrounding region that in turn induces a pressure variation. This propagates an ultrasound signal (MHz range) whose time-of-flight measurement aims to detect the BP position with very high accuracy (<;1mm). This paper presents the simulation results of complete mixed-signals and mixed-energies model that starting from proton beam energy calculates the induced pressure variation in water, emulates the propagation of sound waves in the medium and finally provides a voltage signal (including noise) whose time evolution determines BP position.

 

F. Ciciotti, M. De Matteis and A. Baschirotto, “A 0.9V 600MHz 4th-order analog filter with feed-forward compensated OPAMP in CMOS 28nm”, 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Giardini Naxos, 2017, pp. 265-268. doi: 10.1109/PRIME.2017.7974158

Abstract: In this paper a 600MHz 4th order low-pass analog filter in CMOS-28nm is presented. The transfer function is obtained with the cascade of two Active-RC Rauch biquadratic cells. Each cell is based on a novel OPAMP optimized for very high frequency operation achieving a Unity Gain Bandwidth (UGBW) > 7GHz. The developed three stage folded OPAMP exploits a feed-forward compensation technique to maximize bandwidth and an improved Common Mode Feedback Circuit (CMFB) necessary to reduce parasitic poles and to guarantee acceptable CMFB phase margin. The OPAMP is able to manage the very low VDD/VTH ratio of the 28nm process lowering its input common mode voltage in respect with input and output common mode voltage of the whole filter. The prototype consumes 11.4mW from a single 0.9V supply voltage, achieving 600MHz of bandwidth with an in-band integrated noise of 750µVRMS. The IIP3 calculated at 400 and 450MHz is 12.5dBm.

 

C. M. Zhang et al., “Total ionizing dose effects on analog performance of 28 nm bulk MOSFETs”, 2017 47th European Solid-State Device Research Conference (ESSDERC), Leuven, 2017, pp. 30-33. doi: 10.1109/ESSDERC.2017.8066584

Abstract: This paper uses the simplified charge-based EKV MOSFET model for studying the effects of total ionizing dose (TID) on analog parameters and figures-of-merit (FoMs) of 28nm bulk MOSFETs. These effects are demonstrated to be fully captured by the five key parameters of the simplified EKV model. The latter are extracted from the measured transfer characteristics at each TID. Despite the very few parameters, both the simplified large- and small-signal models present an excellent match with measurements at all levels of TID. The impacts of TID on essential parameters, including the drain leakage current, the threshold voltage, the slope factor, and the specific current, are then evaluated. Finally, TID effects on the transconductance Gm, the output conductance Gds, the intrinsic gain Gm/Gds and the transconductance efficiency Gm/Id are investigated.

2016

F. Resta, A. Pipino, A. Pezzotta, M. De Matteis, M. Croce and A. Baschirotto, “A 4.3µ 28nm-CMOS pixel front-end with switched inverter-based comparator,” 2016 IEEE SENSORS, Orlando, FL, 2016, pp. 1-3. doi: 10.1109/ICSENS.2016.7808899

Abstract: The complete design and electrical characterization of a readout frontend for high luminosity pixel detectors is hereby presented. The design has been carried out in 28nm bulk-CMOS technology. The selected technology process shows significant advantages in terms of radiation hardness, faster/low-power digital signal processing and whole chip area reduction. Nonetheless, it is challenging in terms of operating point (0.9V supply voltage at 0.5V threshold voltage for standard process transistors), dynamic range, and large sensitivity to Process-Voltage-Temperature variations. The proposed integrated circuit includes the cascade of a low-noise preamplifier stage and a switched-capacitor inverter-based comparator. The overall system detects input charges up to 14fC and provides information about the amount of the charge with a Time-over-Threshold (ToT) technique. It features 4.3µ power consumption, 54dB Signal Noise Ratio and 0.02mm2 area occupancy. A ToT range of 180ns in 28nm bulk-CMOS represents a challenge for the future Time-to-Digital Converters (TDC) used in High-Energy-Physics readout systems. Analog front-end and TDC development anticipate a higher charge quantization resolution in the next physics experiments.

 

A. Pezzotta et al., “Impact of GigaRad Ionizing Dose on 28 nm bulk MOSFETs for future HL-LHC,” 2016 46th European Solid-State Device Research Conference (ESSDERC), Lausanne, 2016, pp. 146-149. doi: 10.1109/ESSDERC.2016.7599608

Abstract: The Large Hadron Collider (LHC) running at CERN will soon be upgraded to increase its luminosity giving rise to radiations reaching the level of GigaRad Total Ionizing Dose (TID). This paper investigates the impact of such high radiation on transistors fabricated in a commercial 28 nm bulk CMOS process with the perspective of using it for the future silicon-based detectors. The DC electrical behavior of nMOSFETs is studied up to 1 Grad TID. All tested devices demonstrate to withstand that dose without any radiation-hard layout techniques. In spite of that, they experience a significant drain leakage current increase which may affect normal device operation. In addition, a moderate threshold voltage shift and subthreshold slope degradation is observed. These phenomena have been linked to radiation-induced effects like interface and switching oxide traps, together with parasitic side-wall transistors.

 

A. Pipino, M. De Matteis, A. Pezzotta, F. Resta, S. D’Amico and A. Baschirotto, “A 22.5MHz 21.5dBm-IIP3 4th-Order FLFB analog filter,” ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, 2016, pp. 289-292. doi: 10.1109/ESSCIRC.2016.7598299

Abstract: A 4th-order single-loop Follow-the-Leader-Feedback (FLFB) low-pass filter is hereby presented. The outstanding FLFB noise behavior has been exploited to release a specific power budget for linearity performance enhancement. Moreover, two pairs of complex poles are synthesized by using a single compact Active-RC cell, avoiding cascade of two or more stages (typically needed for high order filters), and relaxing this way noise power constraints. A prototype of the filter has been integrated in CMOS 0.18µm technological node, having 22.5MHz -3dB low-pass frequency. 21.5dBm in-band IIP3 and 76µVRMS input referred in-band integrated noise have been achieved. The SNR for a -40dB-THD is 69dB. The power consumption is 7mA. The efficiency of the hereby proposed technique is demonstrated by the very high Figure-of-Merit (160J-1) achieved by the FLFB filter comparing with the Active-RC filters state-of-the-art.

 

M. De Matteis, F. Resta, A. Pipino, S. D’Amico and A. Baschirotto, “A 28.8-MHz 23-dBm-IIP3 3.2-mW Sallen-Key Fourth-Order Filter With Out-of-Band Zeros Cancellation,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 12, pp. 1116-1120, Dec. 2016. doi: 10.1109/TCSII.2016.2619068

Abstract: In this brief, a 28.8-MHz -3-dB frequency low-pass analog filter is presented. The filter synthesizes a fourth-order Butterworth transfer function, exploiting the well-known Sallen-Key (SK) biquadratic cell. The out-of-band zeros typically present in SK implementations are hereby completely canceled by using a low-power auxiliary path. This leads to a significant improvement of the stop-band rejection, at the cost of a small power for the same auxiliary path biasing. The design exhibits very large in-band IIP3 over the entire filter bandwidth (20 dBm at 10 MHz and 11 MHz), at 3.2-mW power consumption. The filter prototype has been designed in CMOS 0.18-µm technological node. The total area occupancy is 0.12 mm2 and the in-band integrated noise is 101 µVRMS.

 

M. De Matteis, F. Resta, A. Pipino, S. D’Amico and A. Baschirotto, “A 28.8MHz 21.1dBm-IIP3 3.2mW Sallen-Key 4th-Order filter with out-of-band zeros cancellation,” 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, 2016, pp. 2902-2902. doi: 10.1109/ISCAS.2016.7539205

Abstract: A 4th-order 28.8MHz low-pass analog filter uses a modified version of Sallen-Key (SK) biquad that solves the standard SK cell critical aspect due to the out-of-band zeros (OoB). The proposed cell completely cancel the OoB zeros by means of a low-power auxiliary path and a specific design optimization.

 

C. M. Zhang et al., “GigaRad total ionizing dose and post-irradiation effects on 28 nm bulk MOSFETs,” 2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/RTSD), Strasbourg, 2016, pp. 1-4. doi: 10.1109/NSSMIC.2016.8069869

Abstract: The DC performance of both n- and pMOSFETs fabricated in a commercial-grade 28 nm bulk CMOS process has been studied up to 1 Grad of total ionizing dose and at post-irradiation annealing. The aim is to assess the potential use of such an advanced CMOS technology in the forthcoming upgrade of the Large Hadron Collider at CERN. The total ionizing dose effects show limited influence in the drive current of all the tested nMOSFETs. Nonetheless, the leakage current increases significantly, affecting the normal device operation of the nMOSFETs. These phenomena can be linked to the charge trapping in the oxides and at the Si/oxide interfaces, related to both the gate oxide and the shallow trench isolation oxide. In addition, it has been observed that the radiation-induced effects are partly recovered by the long-term post-irradiation annealing. To quantify the total ionizing dose effects on DC characteristics, the threshold voltage, subthreshold swing, and drain induced barrier lowering have also been extracted for nMOSFETs.

 

A. D’Amico, F. Brugger, D. HÃrle, L. Petruzzi and A. Baschirotto, “A 10 bit A-to-D converter development within power optimized BCD technology,” 2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Lisbon, 2016, pp. 1-4. doi: 10.1109/PRIME.2016.7519505

Abstract: This paper presents the development of a 10b ADC dedicated to the digitalization of a sensing current within advanced automotive applications. The presented ADC has been developed in a power optimized BCD technology, i.e. a process specifically optimized for power delivery and featuring signal processing capabilities. However it presents some limitations, i.e. highly non-linear capacitances, large mismatch, etc.. In this scenario a 10b ADC has been developed by means of a customized MATLAB model enabling the target performance achievements. The aim of this work is to study the effect of non-ideal components on the conversion performances focusing in particular on the technology limitations, like capacitors non-linearity and components mismatch. In order to achieve this, a Matlab model has been developed and then a demonstrator circuit has been designed at transistor level.

 

T. Vergine, M. De Matteis, S. Michelis, G. Traversi, F. De Canio and A. Baschirotto, “A 65 nm Rad-Hard Bandgap Voltage Reference for LHC Environment,” in IEEE Transactions on Nuclear Science, vol. 63, no. 3, pp. 1762-1767, June 2016. doi: 10.1109/TNS.2016.2550581

Abstract: A radiation-hard BGR (bandgap voltage reference) circuit is here presented. It’s able to maintain the output voltage accuracy over process, voltage, and temperature (PVT) variations, combined with extremely high total-ionizing-dose (up to 800 Mrad (SiO2)), as required by the next experiments upgrades of the Large Hadron Collider (LHC). The design has been dealt starting from several experimental results, collected from some testing devices, under radiation exposure. In particular, this information has been used modifying the model files provided by foundry, in order to consider the radiation exposure effects during the design process. Consequently, a rad-hard optimized sizing device has been devised. In addition, a particular layout solution has guaranteed a better radiation immunity for the temperature sensing elements (i.e., diodes). The bandgap reference circuit has been fabricated in a commercial 65 nm CMOS technology. Measurement results show a temperature coefficient of about 130 ppm/°C over a temperature range of 120 °C (from -40 °C to 80 °C, as required by application) and a variation of 0.3% for Vdd 1.08 V-1.32 V. The mean value of the BGR output is about 330 mV, with a 10% maximum shift when exposed up to 800 Mrad (SiO2). The power consumption is 240 µW at room temperature, with a core area of 0.018 mm2.